In fabricating microelectronic semiconductor devices on a wafer substrate or chip, such as of silicon, to form an integrated circuit (IC), various metal layers and insulation layers are deposited in selective sequence. To maximize integration of device components in the available substrate area to fit more components in the same area, increased IC miniaturization is utilized. Reduced pitch dimensions are needed for denser packing of components per present day very large scale integration (VLSI), e.g., at sub-micron (below 1 micron, i.e., 1,000 nanometer or 10,000 angstrom) dimensions.
Redundancy techniques are used in semiconductor fabrication to provide deliberate duplication of circuit components to decrease the probability of a circuit failure and thus increase circuit reliability. To offset defects that can occur in the circuitry, multiple copies of a given circuit component are connected in parallel to achieve continued operation upon failure of a particular component. Each such multiple component is provided with a set of fuses that can be blown to replace a failed component by a duplicate one during fusing operation of redundancy activation, e.g., at final IC chip testing.
Some ICs have conductive links between semiconductor devices that are coupled to fuses that can be laser cut (blown) after fabrication. Thus, in a dynamic random access memory (DRAM) circuit, fuses can protect transistor gate stacks from destruction due to inadvertent build-up charges. After IC fabrication, the fuses can be blown to permit the DRAM circuit to function as if the protective current paths never existed.
Also, fuses are used to set the enable bit and the address bits of a redundant array element in a DRAM circuit. To replace a defective main memory array element within a main memory array, a redundant array is provided which has a plurality of fuses in a fuse array coupled thereto via a fuse latch array and a fuse decoder array. In replacing a defective main memory array element, individual fuses in the fuse array are blown to set their values to either a "1" or a "0" required by the decoder circuit. During operation, the values of the fuses in the fuse array are loaded into the fuse latch array upon power up, and these values then decoded by the fuse decoder circuit during run time. This facilitates replacement of specific failed main memory array elements by specific redundant elements of the redundant array, all by well known techniques.
In particular, high density DRAMs are commonly designed with memory cell redundancy whereby the redundant memory cells avoid loss of an entire memory in the event that a minor number of memory cells fail to function. Redundant memory cell activation is effected by blowing fuses selectively placed throughout the memory. Blowing a set of fuses disables the defective memory cell and enables in its place a redundant memory cell.
Fuses may also be incorporated in an IC of a semiconductor device module adapted for custom wiring operation, depending on the requirements of the end user. By blowing selective fuses in the circuit, the semiconductor device module can be customized for particular purposes.
Fuse blowing is effected by heating the fuse to melt it and create an open circuit, e.g., to replace a defective memory cell or other component by a functional cell or different component. The fuse is usually of aluminum, copper or other highly conductive metal or metal alloy, and has a central portion or fuse segment (fuse link) of smaller cross sectional area than its ends (connector terminals) to reduce the energy needed to melt the fuse and create an open circuit condition.
The melting (blowing) of fuses can be effected by a laser beam with a controlled beam width. This can result in laser-induced damage to the area beneath the fuse link, mainly due to absorption of laser energy. Alternatively, electrical fuses can be blown by applying a high current thereto for heating the fuse link by electrical power without such damage.
To enable electrical fusing with voltages below about 10 volts in semiconductor devices, it is important that the cross sectional area reduction from the connector terminals to the electrical fuse segment (fuse link) be as large as possible, preferably greater than 5 or 10. However, the need for such large connector terminals limits the proximity of neighboring fuses.
The voltage necessary to activate an electrical fuse is very sensitive to the geometry of the fuse. The shape of the fuse, its linearity, and the size of the connector terminals all impact the voltage needed to blow the fuse. It is, therefore, important that the fuse geometry be optimized.
An electrical fuse is basically an expendable overcurrent protective device having a circuit-opening fusible (meltable) conductive, e.g., metal or metallic material, fuse segment (fuse link) heated and destroyed by passing an overcurrent through it. The overcurrent heats the fuse link beyond the normal level of radiation loss of the generated resistance heat that keeps its temperature below that at which it melts. The fuse link resistance is particularly determined by the material of which it is made, its cross sectional area, its length, and its temperature.
Like any electrically conductive wire (and apart from the material of which it is made and its temperature), if the length of a fuse link or connector terminal is doubled, its resistance is also doubled, whereas if its cross sectional area is doubled, its resistance is halved. In short, the resistance of a fuse link or connector terminal is directly proportional to its length and inversely proportional to its cross sectional area.
Some examples of the fabrication of semiconductor devices with fuse arrangements are shown in the following prior art.
[1] U.S. Pat. No. 4,635,345 (Hankins et al.), issued Jan. 13, 1987, discloses vertical (three-dimensional), as opposed to horizontal (two-dimensional), fuses in an IC memory array to increase the component density on a substrate in a semiconductor device. A thin oxide fusible element (fuse link) is provided between the emitter region of a bipolar resistor, which emitter forms a bottom electrode (bottom connector terminal), and a top electrode (top connector terminal), e.g., of aluminum. Applying a voltage, e.g., of 12-14 volts, between the top electrode and emitter blows the thin oxide fuse, causing the top electrode to come into contact with the emitter. This is also referred to as anti-fuse.
[2] U.S. Pat. No. 5,436,496 (Jerome et al.), issued Jul. 25, 1995, discloses an array of vertical fuses in an IC to increase the substrate component density in a semiconductor device. Each fuse is selectively permanently programmable after fabrication and the fuse structure includes a buried collector, an overlying base and an emitter above the base and having a metal contact, e.g., of aluminum, at its upper surface. Heating the metal contact/emitter interface to its melting point by a current or voltage pulse causes the aluminum to short through the emitter to the base, thereby programming the fuse. The vertical fuse functionally changes from a floating base transistor to a diode.
[3] Japanese Patent Document JA 403124047 (Saito) of May, 1991, per English Abstract, discloses a polycrystalline silicon fuse link in a vertical U-shaped arrangement in an IC on a substrate to increase the fuse length within a confined substrate area in a semiconductor device.
[4] U.S. Pat. No. 5,313,424 (Adams et al.), issued May 17, 1994, discloses a semiconductor substrate having an electrically blown fuse circuit based on anti-fuse technology. A resistance decrease, e.g., of only 50%, due to dopant redistribution, is exhibited on "blowing" a given fuse. A redundancy system includes circuits to test a memory array to locate a faulty element therein, a resistor to store an address of the faulty element and electrical fuses blown in response to binary digits of the address stored in the register on applying an enable signal from a single input to the semiconductor device. Programmable redundancy is provided by sensing resistance decreases due to dopant redistribution, e.g., in a polysilicon fuse link, in a programmable anti-fuse circuit.
[5] U.S. Pat. No. 5,420,456 (Galbi et al.), issued May 30, 1995, discloses a fuse link with a bend to reduce the power needed for driver transistors to blow the fuse to implement redundancy activation wiring or custom wiring in an IC on a substrate during semiconductor fabrication. Using stated blow control circuitry, the fuse can be blown with only about 10% of the input current density needed for a straight fuse of equal cross sectional area. This is due to current crowding at the bend inside corner which accentuates the current density and thus causes melting at the inside corner. This is enhanced by melt notching which occurs at the bend and causes the fuse link melting to propagate across the fuse link width. The contents of this patent are incorporated herein by reference.
It is known that the shape of an electrical fuse used in a semiconductor device can be changed to lower the voltage needed to blow the fuse. The fuse generally has a pair of connector terminals interconnected by a central fuse link. The fuse can have connector terminals of minimum fuse pitch cross sectional area and a fuse link of reduced cross sectional area to promote some differential resistance heating and some preferential melting of the fuse link.
Secondly, e.g., as noted in said [5] U.S. Pat. No. 5,420,456 (Galbi et al.), issued May 30, 1995, the reduced cross sectional area fuse link of the minimum fuse pitch connector terminal arrangement can be bent to promote even more local preferential melting thereat.
Thirdly, the cross sectional area of the connector terminals can be increased above the minimum fuse pitch to maximize the difference between the cross sectional area of the connector terminals and that of the fuse link to promote maximized differential resistance heating and maximized preferential melting of the fuse link. However, this maximized preferential melting of the fuse link occurs at the expense of the fuse pitch in the semiconductor device circuit because the increase in cross sectional area of the connector terminals limits the closeness of adjacent fuses in the given circuit arrangement.
It is desirable to have a redundancy activation circuit arrangement or other circuit arrangement with fuses of optimum geometry that enable electrical fusing at voltages of at most about 10 volts, and preferably below 10 volts, without limiting the proximity of a given fuse to neighboring fuses or compromising the desired maximum pitch reduction between adjacent fuses.